/*
 * T5.c
 *
 *
 * Timer 5A is set to generate an interrupt every 250ms
 *
 *
 *
 *  Created on: 07/03/2013
 *      Author: Bowmer
 */

#include "inc/lm4f120h5qr.h"

void Timer5_Init(void){


	/**********************/
	/*  Configure TIMER0  */
	/**********************/

	/* Enable Wide TIMER5 peripheral */
	SYSCTL_RCGCWTIMER_R |= SYSCTL_RCGCWTIMER_R5;

	/* Disable Timers A and B */
	WTIMER5_CTL_R &= ~(0x00000101);
	/* 32 bit timer */
	WTIMER5_CFG_R = 0x00000004;
	/* Configure as PWM, continuous, interrupt enabled */
	WTIMER5_TAMR_R = 0x0000020A;

	/* Timer 5A generates on rising edges */
	WTIMER5_CTL_R |= 0x00000000;

	/* Invert the output on Timer5A-PWM */
	WTIMER5_CTL_R |= 0x0000040;

	/* Timer 5A and Timer5B Event Interrupts Enabled */
	WTIMER5_IMR_R = 0x00000004;

	/* 48 bit match value - TAPR contains bits 32-47, TAMATCHR contains bits 0-31 */
	/* Given fCPU 40MHz, need period of 250ms */
	/* 40E6*0.250 = 0d10000000 = 0x00989680*/
	WTIMER5_TAPR_R = 0x0000;
	WTIMER5_TAILR_R = 0x00989680;


	/* 48 bit match value - TAPMR contains bits 32-47, TAMATCHR contains bits 0-31 */
	/* Given fCPU 40MHz, need high time of 0.5ms */
	/* 40E6*0.5E-3 = 0d20000 = 0x00004E20 */
	WTIMER5_TAPMR_R = 0x0000;
	WTIMER5_TAMATCHR_R = 0x00004E20;


	// Enable Timer5A interrupts in the NVIC
	NVIC_EN3_R |= NVIC_EN0_INT8;


	/* Enable Timer 1A */
	WTIMER5_CTL_R |= 0x00000001;

}


